1. Field of the Invention
The present invention relates to a MOS dynamic RAM (DRAM) and, more particularly, to a DRAM with (1/2) V.sub.CC precharge.
2. Description of the Prior Art
It is very important to reduce the power consumed by a DRAM and to shorten the response time in order to arrange a high-density DRAM. In the active state of a DRAM, a large number of bit line pairs are simultaneously charged and discharged. Several hundreds to several thousands of bit line pairs which are simultaneously charged and discharged in a recent high-density DRAM. The charge/discharge current consumption of the bit lines is 50% or more of the entire power consumed by the DRAM. In order to reduce the charge and discharge currents of the bit lines, a (1/2) V.sub.CC precharge scheme is employed to precharge the bit lines to (1/2) V.sub.CC Another technique for reducing charge and discharge currents of bit lines in a DRAM is available to charge and discharge the bit lines in units of sub cell arrays. However, this technique undesirably results in an increase in chip size.
Still another technique is proposed by M. Takada wherein a limiter circuit for setting a bit line charge level to a voltage lower than the power-supply voltage V.sub.CC so as to reduce bit line charge and discharge currents of the DRAM and assure reliability of micro-patterned MOS transistors (IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. sc-21, NO. 5, Oct., 1986). According to this technique, low internal voltage V.sub.BLS, lower than external power-supply voltage V.sub.CC is used to precharge bit lines to a voltage of (1/2) V.sub.BLS lower than (1/2) V.sub.CC.
This technique, however, has the following drawbacks. First, since the precharge voltage is lower than (1/2) V.sub.CC, i.e., since the operation center of bit line charging/discharging is lowered, the operation margin of a bit line sense amplifier is decreased. A DRAM bit line sense amplifier comprises: a PMOS sense amplifier constituted by a flip-flop consisting of two p-channel MOS transistors to amplify a signal of "H" level; and an NMOS sense amplifier constituted by a flip-flop consisting of two n-channel MOS transistors to amplify a signal of "L" level. In this bit line sense amplifier, when a precharge voltage is set at a voltage lower than (1/2) V.sub.CC, the gate-source voltage of these sense amplifiers are lowered. In particular, a decrease in operating margin of the NMOS sense amplifier which amplifies the "L" level signal degrades circuit reliability. Second, when internal voltage V.sub.BLS is fixedly used as a power supply, a forcible acceleration test for testing reliability of a DRAM upon application of a high voltage to an external power supply V.sub.CC terminal cannot be performed. In addition, since internal voltage V.sub.BLS is used as an "H" level voltage in place of external power-supply voltage V.sub.CC, a complicated circuit for stabilizing internal voltage V.sub.BLS is required.